First generation emulation systems were typically formed using general purpose field programmable gate arrays (FPGAs) without integrated debugging facilities. To emulate a circuit design on one of such emulation systems, the circuit design would be “realized” by compiling a formal description of the circuit design, partitioning the circuit design into subsets, mapping the various subsets to the logic elements (LEs) of the FPGAs of various logic boards of the emulation system, and then configuring and interconnecting the LEs. The partitioning and mapping operations would be typically performed on workstations that were part of or complementary to the emulation systems, while the configuration information would be correspondingly downloaded onto the logic boards hosting the FPGAs, and then onto the FPGAs themselves.
With advances in integrated circuit and emulation technology, later emulation systems employed special custom-designed FPGAs specifically for emulation purposes. These special FPGAs typically would include a substantial number of resources such as on-chip reconfigurable logic elements, interconnects, memory, and debugging resources. As the advances continued, more of these resources were packed into each FPGA. As a result, more control signals had to be transferred onto each logic board (for transfer into the FPGAs) to configure the FPGAs. Thus, the amount of configuration data that needed to be transferred from the compile workstation to configure the emulation resources has continued to increase. Likewise, more information about the states of the logic elements needed to be transferred out of the FPGAs and logic boards to facilitate analysis, leading to bottlenecks, in particular at the logic boards, preventing efficient operation of the emulation systems.
For at least these reasons, an improved configuration technique and approach to forming and operating emulation systems is desired.